The present application relates to a memory cell, and more particularly to an integrated-injection logic (I2L) static random access memory (SRAM) cell that includes semiconductor-on-insulator (SOI) symmetrical bipolar transistors.
Integrated-injection logic (I2L) (sometimes also referred to as merged-transistor logic, MTL) technology presents a large potential for high-density and low-power static random access memory (SRAM) since it offers a very compact device structure and a nearly ideal nonlinear load device with a large impedance range (typically 102 to 108 ohms).
I2L is a class of digital circuits built with multiple collector bipolar transistors. The heart of an I2L circuit is the common emitter open collector inverter. Typically, an inverter consists of an NPN transistor with the emitter connected to ground and the base biased with a forward current. The input is supplied to the base, while the output of an inverter is at the collector. To understand how the inverter operates, it is necessary to understand the current flow. If the bias current is shunted to ground (low logic level), the NPN transistor turns off and the collector floats (high logic level). If the bias current is not shunted to ground because the input is high-z (high logic level), the bias current flows through the transistor to the emitter, switching on the transistor, and allowing the collector to sink current (low logic level). Because the output of the inverter can sink current but cannot source current, it is safe to connect the outputs of multiple inverters together to form a wired AND gate.
Digital bipolar transistors using vertical transistors are fast, with circuit delays reaching sub-5 ps. However, the large power dissipation makes vertical bipolar transistors not suitable for VLSI applications. As such, there is a need for providing an I2L SRAM cell in which the power dissipation issue has been circumvented.